Samsung has added a new manufacturing technology into its roadmap. The 11LPP fabrication process is designed for mainstream and higher-end smartphone SoCs. The technology will come online next year and will build upon the company’s 14- as well as 10 nm-branded process technologies.

The Samsung 11LPP process is another hybrid process technology designed to speed up migration from one node to another by Samsung Foundry. Notably, the new node is not another 14LPP-based offering featuring 20 nm BEOL (back end of line) interconnects. Instead 11LPP is based on Samsung’s 10 nm BEOL and therefore enables smaller chips than technologies based on Samsung's 14 nm-branded offerings. Meanwhile, the 11LPP still uses some of the elements featured by Samsung's 14LPP fabrication process.

Last October Samsung began to produce ICs using its 10LPE (10 nm low-power early) manufacturing tech and these days Samsung is getting ready to start producing semiconductors using its 10LPP (10 nm low power plus) process. The company uses both fabrication technologies to make leading edge SoCs for smartphones and other devices, whereas mainstream, low-power and compact chips are to be products using its 14 nm-branded technologies.

The 11LPP will fill the gap between the 10 nm and 14 nm-based offerings. The technology is designed primarily to increase transistor density and provide further improvements on the frequency, transistor count and, to some degree, power consumption fronts. Samsung promises that it will deliver up to 15% higher performance compared to the 14LPP at the same transistor count and power. Furthermore, the 11LPP will enable up to a 10% area reduction at the same transistor count when compared to the 14LPP. In addition, the 11LPP will enable higher transistor density when compared to the 14LPP fabrication process.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
vs 28LPP
vs 14LPE
vs 14LPP
vs 10LPE
vs 14LPP
Power 60% 40% 30% ~15% ?
Performance 40% 27% >10% ~10% 15%
Area Reduction 50% 30% 30% none 10%

Sometime next year, the company intends to start producing its most advanced SoCs using its 7LPP technology featuring EUV for select layers and thus speeding up their cycle times. Meanwhile, the introduction of the first commercial EUV process is not going to stop evolution of DUV technologies. In the coming quarters, Samsung intends to introduce its 14LPU and 10LPU fabrication processes for ultra-low-power applications as well as its all-new 11LPP, which will enable existing customers to shrink their SoCs.

Samsung expects to begin production using its 11LPP manufacturing technology in the second half of 2018. Exact 11LPP high-volume manufacturing schedule of Samsung’s customers depends on their plans.

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Source: Samsung

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  • Anton Shilov - Thursday, October 5, 2017 - link

    The 10 nm BEOL claim comes from Samsung Foundry.
    We are still investigating other peculiarities of the technology, but Samsung makes it clear that the 11LPP is not another 20nm BEOL-based process technology.
  • saayeee - Tuesday, October 3, 2017 - link

    Thanks! this makes more sense.
  • saratoga4 - Saturday, September 30, 2017 - link

    >I mean, they are on a second gen 10nm, but we can just move 14nm designs to 10nm?

    Yes, provided you can afford it. For budget parts, slightly lower performance may be a small price to pay for cost savings and higher yields.
  • HStewart - Friday, September 29, 2017 - link

    I would like a comparison of technology - include transistor count per square area.
  • FreckledTrout - Friday, September 29, 2017 - link

    I have seen a few done by engineers but the comparisons vary based on what you compare as some processes tend to make desnor simpler things like SRAM and some processes tend to made denser complex things like CPU. It's a difficult idea to try to predict the end result from process specifications.
  • Ian Cutress - Friday, September 29, 2017 - link

    Something like this, but with processes labeled I'd imagine.

    Check out @IanCutress’s
  • Wilco1 - Saturday, September 30, 2017 - link

    That graph seems quite incorrect - 10nm TSMC is already at 60 million transistors per mm^2, 7nm will be 116 (

    Also interesting is the standard node comparison: (although those graphs don't show the 10nm delays for Intel).
  • Lord-Bryan - Saturday, September 30, 2017 - link

    Is the first link a paywalled article?
  • saratoga4 - Saturday, September 30, 2017 - link

    No, just the forums software ate the link. Try this:
  • Lord-Bryan - Sunday, October 1, 2017 - link


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