One of the key metrics on how well a semiconductor process is developing is looking at its quantitative chip yield – or rather, its defect density. A manufacturing process that has fewer defects per given unit area will produce more known good silicon than one that has more defects, and the goal of any foundry process is to minimize that defect rate over time. This will give the customers better throughput when making orders, and the foundry aims to balance that with the cost of improving the manufacturing process.

The measure used for defect density is the number of defects per square centimeter. Anything below 0.5/cm2 is usually a good metric, and we’ve seen TSMC pull some really interesting numbers, such as 0.09 defects per square centimetre on its N7 process node only three quarters after high volume manufacturing started, as was announced in November at the VLSI Symposium 2019. As it stands, the defect rate of a new process node is often compared to what the defect rate was for the previous node at the same time in development. As a result, we got this graph from TSMC’s Technology Symposium this week:

As it stands, the current N5 process from TSMC has a lower defect density than N7 did at the same time in its development cycle. TSMC. This slide from TSMC was showcased near the start of the event, and a more detailed graph was given later in the day:

This plot is linear, rather than the logarithmic curve of the first plot. This means that TSMC’s N5 process currently sits around 0.10 to 0.11 defects per square centimeter, and the company expects to go below 0.10 as high volume manufacturing ramps into next quarter.

Part of what makes 5nm yield slightly better is perhaps down to the increasing use of Extreme UltraViolet (EUV) technology, which reduces the total number of manufacturing steps. Each step is a potential chance to decrease yield, so by replacing 4 steps of DUV for 1 step of EUV, it eliminates some of that defect rate.

TSMC’s first 5nm process, called N5, is currently in high volume production. The first products built on N5 are expected to be smartphone processors for handsets due later this year.

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  • Guspaz - Tuesday, August 25, 2020 - link

    Apple's probably bigger, but between their multi-die CPUs, their GPUs, their APUs, their console chips, AMD's still making a ton of dies with TSMC. They did collaborate on a semi-custom node, after all. Reply
  • melgross - Tuesday, August 25, 2020 - link

    Whatever AMD does, Apple is still TSMC’ s largest customer, by some margin. It’s possible that Qualcomm is number two, or close to it. Reply
  • Valantar - Tuesday, August 25, 2020 - link

    There's some nuance to be had here though. Apple is likely still TSMC's biggest customer, and the one most willing to pay whatever is needed for first access, but AMD shouldn't be that far behind in terms of volume, at least in the immediate future. How? Apple's SoCs are generally below 100mm2 (often quite a lot below). AMD' s CCDs are small, but they also make GPUs and console SoCs - and the latter are going to need a lot of wafers in the next couple of years. 20 million console SoCs - a likely sales number at least for the first year or two - would likely require as many wafers as something like a quarter of Apple's phone and tablet SoCs. Then there's consumer and datacenter GPUs, the vast majority of which will also be on the large side, and the ever growing sales of Ryzen. In other words, there's reason to believe that AMD is getting close to Apple in terms of sheer wafer volume. Reply
  • canukstorm - Tuesday, August 25, 2020 - link

    Every SoC Apple designs (iPhone, iPad, iPad Pro, AirPods, HomePod, Watch) is manufactured by TSMC. That's approximately 250 million devices per year. And AMD doesn't contract out to only TSMC. They also contract out to GlobalFoundries. Reply
  • melgross - Tuesday, August 25, 2020 - link

    TSMC makes more for Apple than just SoCs. They make Apple’s video controller chips, the t2 for Macs, various other sensor and controller chips. Over all, the number is easily close to, if not more than 300 million. It’s not just number of wafers that determine value. That’s an oversimplification. Reply
  • Wilco1 - Wednesday, August 26, 2020 - link

    250 million 100mm^2 mobile SoCs would be close to 500000 7nm wafers per year. Reply
  • astroboy888 - Wednesday, August 26, 2020 - link

    Not sure about volume for each company. But in terms of projected revenue for 2021, Apple is paying TSMC about $11 billion USD almost 1/3 of TSMC's total revenue. giving them 1st place by a long shot. 2nd place is AMD with projected revenue share of $4.6 billion USD. Then there are a bunch of $2 and 3billions customers, including Broadcom, Qualcomm, Nvidia ... etc. Reply
  • Spunjji - Wednesday, August 26, 2020 - link

    @melgross here counting chips because they know Apple build smaller chips than AMD and therefore it makes their numbers look bigger. 😏 Reply
  • melgross - Wednesday, August 26, 2020 - link

    No. As was just pointed out, Apple is one third of TSMC’ s revenue. Nobody else comes close. Reply
  • smalM - Saturday, August 29, 2020 - link

    Apple is TSMC's biggest customer at $8.0Bn 2019, $7.4Bn 2018, and $7.4Bn 2017.
    This is directly from their financial report for 2019.
    Reply

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