AMD Discloses Bobcat & Bulldozer Architectures at Hot Chips 2010by Anand Lal Shimpi on August 24, 2010 1:33 AM EST
Three years ago AMD told me about two architectures that would be the future of the company: Bobcat and Bulldozer. Here are some excerpts from an article I wrote after that meeting with AMD.
“Due out in the first half of 2009, AMD's Bulldozer core is the true revolutionary successor to the K8 architecture. While Barcelona and Shanghai are both evolutionary improvements to the current core, Bulldozer is the first ground-up redesign since the K7.”
“If Bulldozer is the architecture that will compete with Nehalem, Bobcat is what will compete with Silverthorne. Bobcat is yet another ground up design from AMD, also due out in the 2009 timeframe, but it will address a more power constrained portion of the market. Systems that require a 1 - 10W TDP will use Bobcat, while Bulldozer is limited to the 10 - 100W range (obviously with some overlap between the two). “
Well, 2009 didn’t happen. Nor will 2010. Bobcat is the closest with production in Q4 2010 and system availability in Q1 2011. Bulldozer is strictly 2011. The long road to a major redesign isn’t unusual and although we’re no where near the point of measuring performance of these parts, we’re getting closer.
AMD has Bobcat and Bulldozer silicon back in its labs and things apparently look good. Later today at Hot Chips 22, AMD will present further details on both of its next generation architectures. What we have here now is a sneak peak of what AMD is going to unveil at the conference later today.
The Three Chip Roadmap
While AMD is committed to a two architecture roadmap going forward (Bobcat and Bulldozer) we’ll see three fairly different chips addressing the various market segments in 2011.
Bobcat will do low end/low power (think netbooks and nettops), Llano will do mainstream notebooks (e.g. MacBook, HP Envy equivalent) and Bulldozer will be used for high end desktops and servers. Llano actually uses a Phenom II derived core so it’s technically a third architecture but I’d expect its market to eventually be split between Bobcat and Bulldozer based designs.
I’m going to start with Bobcat first as it’s the closest to production.
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Mr Perfect - Wednesday, August 25, 2010 - linkIt sounds like AMD will be selling by the integer core though, not by module. There's this from Page 4:
"Processors may implement anywhere from one to four Bulldozer modules and will be referred to as 2 to 8 core CPUs."
So they will be referring to four module APUs as having eight cores, rather then a quad core with HyperThreading.
silverblue - Wednesday, August 25, 2010 - linkSorry, I did mean to tackle the part of your thread dealing with different versions of Bulldozer. Valencia is a server version of Zambezi, i.e. 4 modules/8 threads. Interlagos is 8 modules/16 threads.
From AMD's own figures, each module is 1.8 times the speed of a current K10.5 core at the same clock speed. It is a little unfair to compare "core" to core due to the way they're designed and implemented. Considering each K10.5 core has three ALUs and Bulldozer has two per integer core, 90% of that integer performance is very good - for a quad core CPU in the current sense, Bulldozer would theoretically outpace Phenom II by 80% in integer work by only having 33% more integer resources, assuming the chip is well fed. If the rumours about a quad-channel memory bus are correct, you'd hope it would be.
jeremyshaw - Wednesday, August 25, 2010 - linkI believe Intel also delegated some Atom production to TSMC, unless if I am wrong?
Penti - Thursday, August 26, 2010 - linkTSMC also does manufacture VIAs / Centaur Tech x86 processor.
Probably a few others too. There's some x86 SoCs for embedded stuff from other vendors.
Perisphetic - Wednesday, August 25, 2010 - linkIt's time to kick ass and chew bubble gum... and AMD is all outta gum.
NaN42 - Wednesday, August 25, 2010 - linkAt first: I think AMD made a huge progress with Bulldozer.
But I'm wondering how the FPU will work exactly. A look at the latencies (especially of fma-instructions) would be interesting too. Another question is, if it is possible to start one independent multiply and one addition at the same time in a FMAC-unit. Furthermore the throughput is of interest. Is it one mul and add instruction per cycle? Is there any advantage to use 256 bit AVX-instructions, besides shorter code?
I appreciate that AMD will drop most 3Dnow-instructions because these are just outdated. Perhaps they could also drop MMX instructions but maintain x87-instructions because these are sometimes useful and needed.
I expect the decoder besides the FPU (compared to Sandy Bridge) to be another bottleneck because the 4-wide decoder has to feed two nearly independent cores and todays 3-wide decoders (except those in Nehalem/Westmere) are sometimes a bottleneck in a single core design.
@Ontario: I expect this platform to be much more powerful than the Atom platforms. Perhaps it will even be much more efficient than Atom. A direct comparison between Ontario and VIA Nano 3000 might be interesting especially when VIA releases dual core chips.
GourdFreeMan - Thursday, August 26, 2010 - linkIt seems that AMD is ceding the traditional laptop and desktop market to Intel and chasing the server market and Atom/ARM's market with Bulldozer and Bobcat respectively. Lower theoretical peak IPC and greater parallelism target well the high level of data and transaction level parallelism in the server market, but existing consumer software excepting video encoding and a handful of games still tend to favor single threaded performance over parallelism. I suppose we should wait for benchmarks in actual applications to see how well architectural improvements have impacted the performance of AMD's new designs, but I imagine some people are already disappointed. Too bad the resources in both integer cores in a module can't work on a single thread, otherwise we could have had a very serious contender on the desktop...
silverblue - Thursday, August 26, 2010 - linkHe sure seemed confusing on the comments page of his blog a few weeks back. Understandably evasive considering he's a server tech guy, not consumer tech, plus AMD were yet to reveal these details, but he was comparing 16 Bulldozer cores to 12 Magny Cours cores, which is technically incorrect as they're not comparable UNLESS you're talking about integer cores. At least, that's my interpretation.
AMD will probably market Zambezi as an 8-core CPU in order to woo the more-is-better crowd, but regardless of how it handles multi-threading, I still view a module as an actual core virtue of the fact that the "cores" are not independant of the module they belong to. I know I'm wrong and that's fine, but it helps in understanding the technology better - eight cores that exist in pairs and share additional resources might serve to confuse.
gruffi - Thursday, August 26, 2010 - linkA 12-core Magny-Cours has 12 "integer cores" and 12 128-bit FPUs. A 16-core Interlagos has 16 "integer cores" and 16 128-bit FMACs. Why is it technically not comparable? At least you know you are wrong. ;)
silverblue - Friday, August 27, 2010 - linkThe implementation is very different to what AMD have done before, that's what I'm trying to get at. Everyone knew that despite Intel and AMD having different types of quad core processor prior to Nehalem, they were still classed the same so I suppose it doesn't matter in the grand scheme of things. There's nothing to stop AMD from releasing a 24-"core" Bulldozer; it shouldn't be any larger than Magny-Cours - perhaps slightly smaller in the end - yet its integer performance would be through the roof.
However, people are bemoaning the fact that for 33% more "cores", AMD are only getting 50% extra performance - it's worth bearing in mind that AMD does this with 4 less, albeit better utilised ALUs than Magny-Cours (32 compared to 36). Make no mistake, Bulldozer is far more efficient and capable in this scenario, but I can't help wondering how strong Phenom II may have been if it'd had a slightly more elegant design.