Introducing Skylake-SP: The Xeon Scalable Processor Family

The biggest news hitting the streets today comes from the Intel camp, where the company is launching their Skylake-SP based Xeon Scalable Processor family. As you have read in Ian's Skylake-X review, the new Skylake-SP core has been rather significantly altered and improved compared to it's little brother, the original Skylake-S. Three improvements are the most striking: Intel added 768 KB of per-core L2-cache, changed the way the L3-cache works while significantly shrinking its size, and added a second full-blown 512 bit AVX-512 unit. 

On the defensive and not afraid to speak their mind about the competition, Intel likes to emphasize that AMD's Zen core has only two 128-bit FMACs, while Intel's Skylake-SP has two 256-bit FMACs and one 512-bit FMAC. The latter is only useable with AVX-512. On paper at least, it would look like AMD is at a massive disadvantage, as each 256-bit AVX 2.0 instruction can process twice as much data compared to AMD's 128-bit units. Once you use AVX-512 bit, Intel can potentially offer 32 Double Precision floating operations, or 4 times AMD's peak.  

The reality, on the other hand, is that the complexity and novelty of the new AVX-512 ISA means that it will take a long time before most software will adopt it. The best results will be achieved on expensive HPC software. In that case, the vendor (like Ansys) will ask Intel engineers to do the heavy lifting: the software will get good AVX-512 support by the expensive process of manual optimization. Meanwhile, any software that heavily relies on Intel's well-optimized math kernel libraries should also see significant gains, as can be seen in the Linpack benchmark. 

In this case, Intel is reporting 60% better performance with AVX-512 versus 256-bit AVX2. 

For the rest of us mere mortals, it will take a while before compilers will be capable of producing AVX-512 code that is actually faster than the current AVX binaries. And when they do, the result will be probably be limited, as compilers still have trouble vectorizing code from scratch. Meanwhile it is important to note that even in the best-case scenario, some of the performance advantage will be negated by the significantly lower clock speeds (base and turbo) that Intel's AVX-512 units run at due to the sheer power demands of pushing so many FLOPS. 

For example, the Xeon 8176 in this test can boost to 2.8 GHz when all cores are active. With AVX 2.0 this is reduced to 2.4 GHz (-14%), with AVX-512, the clock tumbles down to 1.9 GHz (another 20% lower). Assuming you can fill the full width of the AVX unit, each step still sees a significant performance improvement, but AVX2 to AVX-512 won't offer a full 2x performance improvement even with ideal code.

Lastly, about half of the major floating point intensive applications can be accelerated by GPUs. And many FP applications are (somewhat) limited by memory bandwidth. While those will still benefit from better AVX code, they will show diminishing returns as you move from 256-bit AVX to 512-bit AVX. So most FP applications will not achieve the kinds of gains we saw in the well-optimized Linpack binaries. 

AMD’s EPYC 7000-Series Processors Intel's New On-Chip Topology: A Mesh
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  • Shankar1962 - Wednesday, July 12, 2017 - link

    AMD is fooling everyone one by showing more cores, pci lanes, security etc
    Can someone explain me why GOOGLE ATT AWS ALIBABA etc upgraded to sky lake when AMD IS SUPERIOR FOR HALF THE PRICE?
  • Shankar1962 - Wednesday, July 12, 2017 - link

    Sorry its Baidu
    Pretty sure Alibaba will upgrade
  • PixyMisa - Thursday, July 13, 2017 - link

    Lots of reasons.

    1. Epyc is brand new. You can bet that every major server customer has it in testing, but it could easily be a year before they're ready to deploy.
    2. Functions like ESXi hot migration may not be supported on Epyc yet, and certainly not between Epyc and Intel.
    3. Those companies don't pay the same prices we do. Amazon have customised CPUs for AWS - not a different die, but a particular spec that isn't on Intel's product list.

    There's no trick here. This is what AMD did before, back in 2006.
  • blublub - Tuesday, July 11, 2017 - link

    I kinda miss Infinity Fabric on my Haswell CPU and it seems to only have on die - so why is that missing on Haswell wehen Ryzen is an exact copy?
  • blublub - Tuesday, July 11, 2017 - link

    argh that post did get lost.
  • zappor - Tuesday, July 11, 2017 - link

    4.4.0 kernel?! That's not good for single-die Zen and must be even worse for Epyc!

    AMD's Ryzen Will Really Like A Newer Linux Kernel:

    Kernel 4.10 gives Linux support for AMD Ryzen multithreading:
  • JohanAnandtech - Friday, July 21, 2017 - link

    We will update to a more updated kernel once the hardware update for 16.04 LTS is available. Should be August according to Ubuntu
  • kwalker - Tuesday, July 11, 2017 - link

    You mention an OpenFOAM benchmark when talking about the new mesh topology but it wasn't included in the article. Any way you could post that? We are trying to evaluate EPYC vs Skylake for CFD applications.
  • JohanAnandtech - Friday, July 21, 2017 - link

    Any suggestion on a good OpenFoam benchmark that is available? Our realworld example is not compatible with the latest OpenFoam versions. Just send me an e-mail, if you can assist.
  • Lolimaster - Tuesday, July 11, 2017 - link

    AMD's lego design where basically every CCX can be used in whatever config they want be either consumer/HEDT or server is superior in the multicore era.

    Cheaper to produce, cheaper to sell, huge profits.

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