AMD's EPYC Server CPU

If you have read Ian's articles about Zen and EPYC in detail, you can skip this page. For those of you who need a refresher, let us quickly review what AMD is offering. 

The basic building block of EPYC and Ryzen is the CPU Complex (CCX), which consists of 4 vastly improved "Zen" cores, connected to an L3-cache. In a full configuration each core technically has its own 2 MB of L3, but access to the other 6 MB is rather speedy. Within a CCX we measured 13 ns to access the first 2 MB, and 15 to 19 ns for the rest of the 8 MB L3-cache, a difference that's hardly noticeable in the grand scheme of things. The L3-cache acts as a mostly exclusive victim cache. 

Two CCXes make up one Zeppelin die. A custom fabric – AMD's Infinity Fabric – ties together two CCXes, the two 8 MB L3-caches, 2 DDR4-channels, and the integrated PCIe lanes. That topology is not without some drawbacks though: it means that there are two separate 8 MB L3 caches instead of one single 16 MB LLC. This has all kinds of consequences. For example the prefetchers of each core make sure that data of the L3 is brought into the L1 when it is needed. Meanwhile each CCX has its own separate (not inside the L3, so no capacity hit) and dedicated SRAM snoop directory (keeping track of 7 possible states). In other words, the local L3-cache communicates very quickly with everything inside the same CCX, but every data exchange between two CCXes comes with a tangible latency penalty. 

Moving further up the chain, the complete EPYC chip is a Multi Chip Module(MCM) containing 4 Zeppelin dies.

AMD made sure that each die is only one hop apart from the other, ensuring that the off-die latency is as low as reasonably possible.

Meanwhile scaling things up to their logical conclusion, we have 2P configurations. A dual socket EPYC setup is in fact a "virtual octal socket" NUMA system. 

AMD gave this "virtual octal socket" topology ample bandwidth to communicate. The two physical sockets are connected by four bidirectional interconnects, each consisting of 16 PCIe lanes. Each of these interconnect links operates at +/- 38 GB/s (or 19 GB/s in each direction). 

So basically, AMD's topology is ideal for applications with many independently working threads such as small VMs, HPC applications, and so on. It is less suited for applications that require a lot of data synchronization such as transactional databases. In the latter case, the extra latency of exchanging data between dies and even CCX is going to have an impact relative to a traditional monolithic design.

Tensions (And Chip Sizes) Are Rising AMD’s EPYC 7000-Series Processors
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  • extide - Tuesday, July 11, 2017 - link

    PCPer made this same mistake -- Nehalem/Westmere used a crossbar memory bus -- not a ringbus. Only Nehalem/Westmere EX used the ringbus (the 6500/7500 series) The i7 and Xeon 5500 and 5600 series used the crossbar. Reply
  • extide - Tuesday, July 11, 2017 - link

    Sandy Bridge brought the ringbus down to Xeon EP and client chips. Reply
  • Yorgos - Tuesday, July 11, 2017 - link

    "With the complexity of both server hardware and especially server software, that is very little time. There is still a lot to test and tune, but the general picture is clear."

    No wonder why we see ubuntu and ancient versions of gcc and the rest of the s/w stack.
    Imagine if you tried to use debian or rhel, it would take you decades to get the review.
    Reply
  • eligrey - Tuesday, July 11, 2017 - link

    Why did you omit the Turbo frequencies for the Xeon Gold 6146 and 6144?

    Intel ARK says that the 6146's turbo frequency is 4.2GHz and the 6144's is 4.5GHz.
    Reply
  • eligrey - Tuesday, July 11, 2017 - link

    Oops, I mean 4.2GHz for both. Reply
  • boozed - Tuesday, July 11, 2017 - link

    Need more Skylake-SP SKUs Reply
  • rHardware - Tuesday, July 11, 2017 - link

    For the purley system, It's listed that you used Chipset Intel Wellsburg B0

    This information cannot be correct. Lewisburg Chipset is the name of the purley chipset. Also, B0 stepping lewisburg also wouldn't boot with the stepping of CPU you have.
    Reply
  • rHardware - Tuesday, July 11, 2017 - link

    That 0200011 microcode is also very old. Reply
  • Rickyxds - Tuesday, July 11, 2017 - link

    I'am a brazilian processors enthusiast and I'am very critic about intel and AMD processors, between 2012 and Q1 2017 AMD just doesn't existed, who bought AMD on that years, bougth just for love AMD and just it, doesn't for the price, doesn't for the high core count, doesn't for AMD is red, AMD was the worst performance processors. The A9 Apple dual core performance is better than FX 8150.

    But now I am very surprise with the aggressive AMD prices. No one here Imagined get the Ryzen 7 performance for less than $500. And I don't know if this scenario brings profit to AMD, but for the image against the intel it's wonderful.

    On the next years we will see.
    Reply
  • krumme - Tuesday, July 11, 2017 - link

    Thank you for quality stuff article especially given the short time. So thank you for booting up Johan !

    Interesting and surpricing results.
    Reply

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