Sidebar on Intel EUV

In all of these announcements, one thing to highlight is Intel mentioning its relationship with ASML, the sole company that manufactures the EUV machines powering production of leading edge semiconductor manufacturing.


ASML Wilton

ASML is a unique company in that it is the only one that can produce these machines, because the technology behind them is often tied up with its partners and research, but also because all the major silicon manufacturers are heavily invested in ASML. For any other company to compete against ASML would require building a separate network of expertise, a decade of innovation and design, and a lot of capital. None of the major silicon vendors want to disturb this balance and go off on their own, lest it shuts them out of the latest manufacturing technology, and no research fund sees competing against the embedded norm as a viable opportunity. This means that anyone wanting EUV specialist technology has to go to ASML.

In 2012, it was reported that Intel, Samsung, and TSMC all invested in ASML. This was, at the time, to jumpstart EUV development along with migrating from 300mm wafers to 450mm wafers. While we haven’t moved to 450mm wafers yet (and there are doubts we will any time in the next decade), EUV is now here. Intel’s 2012 investment of $2.1 billion gave them a 10% stake in ASML, with Intel stating that it would continue investing up to a 25% stack. Those stakes are now below the 5% reporting threshold, but all three of the major foundry customers are still big owners, especially as ASML’s market cap has risen from $24 Billion in 2012 to $268 Billion in 2021 (surpassing Intel).

As major investors but also ASML’s customers, the race has been on for these foundries to acquire enough EUV machines to meet demand. TSMC reported in August 2020 that it has 50% of all EUV machines manufactured at ASML for its leading edge processes. Intel is a little behind, especially as none of Intel’s products in the market yet use any EUV. EUV will only intercept Intel’s portfolio with its new Intel 4 process, where it will be used extensively, mostly on the BEOL. But Intel still has to order machines when they need them, especially as there are reports that ASML currently has backorders of 50 EUV machines. In 2021, ASML is expected to manufacture around 45-50 machines, and 50-60 in 2022. The exact number of machines Intel has right now, or has ordered from ASML, is unknown. It is expected that each one has a ~$150m price tag, and can take 4-6 months to install.

With all that being said, Intel’s discussion point today is that it will be the lead customer for ASML’s next generation EUV technology known as High-NA EUV. NA in this context relates to the ‘numerical aperture’ of the EUV machine, or to put simply, how wide you can make the EUV beam inside the machine before it hits the wafer. The wider the beam before you hit the wafer, the more intense it can be when it hits the wafer, which increases how accurately the lines are printed. Normally in lithography to get better printed lines, we move from single patterning to double patterning (or quad patterning) to get that effect, which decreases yield. The move to High-NA would mean that the ecosystem can stay on single patterning for longer, which some have quoted as allowing the industry to ‘stay aligned with Moore’s Law longer’.

ASML's EUV Shipments
  2015 2016 2017 2018 2019 2020 2021
Actual 2 4 10 3 4 5 6 4 7 7 8 4 7 14 8 7 9 - -
Target (Total) - - - 20 (18) 30 (26) 35 (33) 45-50
2018 and beyond is split per quarter for actual shipped numbers
Data taken from ASML's Financial Reports

Current EUV systems are NA 0.33, while the new systems are NA 0.55. ASML’s latest update suggests that it expects customers to be using High-NA for production in 2025/2026, which means that Intel is likely going to be getting the first machine (ASML NXE:5000 we think) in mid-2024. Exactly how many High-NA machines ASML intends to produce in that time frame is unknown, as if they flood the market, having the first won’t be a big win. However if there is a slow High-NA ramp, it will be up to Intel to capitalize on its advantage.

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  • Maksdampf - Tuesday, July 27, 2021 - link

    You know that Intels numbers that they out out haven't been spotted in the wild on any of their products, right? They had been doing these marketing stunts for a while, just with a different disguise. 107MTr/mm2 vor 10SF, my Ass.

    Since Pat has relased some Transistor count figures, we know that cometlake with 4,2BTr and 205mm2 only has a density of around 21MTr/mm2 instead of the claimed 44MTr/mm2 for 14nm++ and even the newest shiniest rocketlake is worse than AMDs original zeppelin design in Density (6BTr on 270mm2 vs 4.8BTr on 192mm2).
    Since Tigerlake-H is only different in its L3 cache system, we know it is around 8-9BTr compared to cypress cove based Rocketlake. And it still has the much larger DIE coming in at 190mm2 compared to AMDs Cezanne with 10,78BTr including a much beefier GPU.

    And this is comparing Apples to Apples, so HP processes to HP, not High density to mobile.
    TSMCs and Samsungs Mobile Processes are in reality so far ahead in Density and Power of anything Intel ships, that you really need an M1 class of chip to show it.

    Intel has us fooled by meaningless laboratory numbers that can nowhere be found in real products for years and now they fuck us over again by renaming those already pretty desperate naming schemes.
    Reply
  • name99 - Tuesday, July 27, 2021 - link

    Not if those transistor estimates never match real products…
    For years now, nothing Intel ships is close to their claimed transistor density. It’s like 2 to 3x off.

    So…
    Reply
  • Butterfish - Tuesday, July 27, 2021 - link

    So does most chip made by other foundries. These figure are for the high density library. If you look at AMD’s CPU and GPU which use TSMC’s high performance library that aren’t optimized for density you will see much lower density number compare to what was advertised for the process nodes they are using. Reply
  • Spunjji - Wednesday, July 28, 2021 - link

    Yes, you will see lower density - but something like 60-80% of the quoted density. Intel are hitting something more like 33-50% of what they quoted for 10nm. Reply
  • cheshirster - Tuesday, July 27, 2021 - link

    Intel hide transistor density of their products since Coffee Lake.
    For years as of now.
    Reply
  • cheshirster - Tuesday, November 23, 2021 - link

    Still Intel, cause their transistors counts aren't disclosed for any 10nm product. Reply
  • IntelUser2000 - Monday, July 26, 2021 - link

    No, Ian lobbied for it.

    Boo!!
    Reply
  • mode_13h - Tuesday, July 27, 2021 - link

    Yeah, as a journalist, he shouldn't be trying to influence the industry. He can ask them questions like how they feel about TSMC/Samsung's node naming, during interviews, but that about as far as it should go. Reply
  • Oxford Guy - Wednesday, July 28, 2021 - link

    I can only assume your post is not particularly well-executed parody of the misguided point of view it’s espousing.

    What a stupid comment.

    Journalists, of course, can (and often should) be more than marketing department parrots, more than stenographers.
    Reply
  • Spunjji - Thursday, July 29, 2021 - link

    I'm always confused by that idea that there's some magical bright line between being a journalist and an enthusiast. Ian can advocate for whatever he wants from Intel - as long as he's actually honest about it, IDGAF. Reply

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