One of the key drivers to increase capacity in next generation storage has been to increase the number of bits that can be stored per cell. The easy jump of one to two bits-per-cell gives a straight 100% increase, in exchange for more control needed to read/write the bit but also limits the cell endurance. We’ve seen commercialization of storage up to four bits-per-cell, and talk about five. A Japanese company is now ready to start talking about their new 7 bits-per-cell solution.

Image courtesy of Plextor, up to 4 bits-per-cell

Moving from one to two bits-per-cell gives an easy doubling of capacity, and moving to three bits-per-cell is only another 50% increase. As more bits are added, the value of adding those bits diminishes, but the cost in the equipment to control the read and writes increases exponentially. There has to be a medium balance between how many bits-per-cell makes economic sense, and how much the control electronics costs to implement to enable those bits.

  • 1 bit per cell requires detection of 2 voltage levels, base capacity
  • 2 bit per cell requires detection of 4 voltage levels, +100% capacity
  • 3 bit per cell requires detection of 8 voltage levels, + 50% capacity
  • 4 bit per cell requires detection of 16 voltage levels, +33% capacity
  • 5 bit per cell requires detection of 32 voltage levels, +25% capacity
  • 6 bit per cell requires detection of 64 voltage levels, +20% capacity
  • 7 bit per cell requires detection of 128 voltage levels, +16.7% capacity

Also, the more bits-per-cell, the lower the endurance – the voltage variation when you store many bits only has to drift slightly to get the wrong result, and so repeated read/writes to a high capacity cell will make that voltage drift until the cell is unusable. Right now the market seems happy with three bits-per-cell (3bpc) for performance and four bits-per-cell (4bpc) for capacity, with a few 2bpc designs for longer term endurance. Some of the major vendors have been working on 5bpc storage, although the low endurance may make the technology only good for WORM – write once, read many, which is a common acronym for the equivalent of something like an old-school CD or non-rewritable DVD.

Floadia Corp., a Series C startup from Japan, issued a press release this week to state that it has developed st­­orage technology capable of seven bits-per-cell (7bpc). Still in the prototype stage, this 7bpc flash chip, likely in a WORM scenario, has an effective 10-year retention time for the data at 150C. The company says that a standard modern memory cell with this level of control would only be able to retail the data for around 100 seconds, and so the secret in the design is to do with a new type of flash cell they have developed.

The SONOS cell uses a distributed charge trap design relying on a Silicon-Oxide-Nitride-Oxide-Silicon layout, and the company points to an effective silicon nitride film in the middle where the charges are trapped to allow for high retention. In simple voltage program and erase cycles, the company showcases 100k+ cycles with a very low voltage drift. The oxide-nitride-oxide layers rely on SiO2 and Si3N4, the latter of which is claimed to be easy to manufacture. This allows a non-volatile SONOS cell to be used in NV-SRAM or embedded designs, such as microcontrollers.

It’s actually that last point which means we’re a long time from seeing this in modern NAND flash. Floadia is currently partnering with companies like Toshiba  to implement the SONOS cell in a variety of microcontrollers, rather than large NAND flash deployments, at the 40nm process node as embedded flash IP with compute-in-memory properties. Those aren’t at 7 bits-per-cell yet, to the effect that the company is promoting that two cells can store up to 8-bits of network weights for machine learning inference – when we get to 8 bits-per-cell, then it might be more applicable. The 10-year retention of the cell data is where it gets interesting, as embedded platforms will use algorithms with fixed weights over the lifetime of the product, except for the rare update perhaps. Even with increased longevity, Floadia doesn’t go into detail regarding cyclability at 7bpc at this time.

An increase from modern 3bpc to 6bpc NAND flash would afford a double density increase, however larger cells would be needed, which would negate the benefits. There’s also the performance aspect if the development of >4bpc ever made it to consumers, which hasn’t been touched upon.

It will be an interesting technology to follow.

Source: Floadia Press Release

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  • back2future - Monday, January 3, 2022 - link

    3d-V-NAND (>2013, vs. planar 2d NAND) improved cell performance (page 12),
    more evenly distributed 'natural' voltage threshold, reduced cell coupling (on read/write ?),
    a 950 PRO's CTF (Charge Trap Flash) technology is advertised like nearly interference-free, wrt to cell coupling and therefore improve longevity and retention performance (?)
  • mode_13h - Tuesday, January 4, 2022 - link

  • back2future - Tuesday, January 4, 2022 - link

    Considering 3d-Xpoint (Intel) there's 'fewer' information about data retention, but some (most) on cell performance (high IOPS for random r/w, write-in-place tech) and (r/)w endurance (TBW ~10x TLC-NAND types and P/E <=1billion-10million).

    If focus changes for newer gen4 SSD's Corsair MP600 gen4 compared to 3d-Xpoint Intel Optane 900p (PCIe 3.x), performance wise they are about on par.
    product examples
    P4800X "The Intel® Optane™ SSD DC P4800X follows the JESD218B-01 standard for data retention: 3 months of powered off retention at 40C. Powered on, data retention is throughout the product warranty period."

    2010 table (so probably all SLC only), weeks for data retention
    ( page 27, )
    active higher temperature on flash generally improves data retention (contrary to power-off retention time decrease)?

    read disturbance comparison Xpoint, 3dNAND (if affected by technology)
    page 14,

    2016/2017 review of Xpoint tech (& Micron QuantX)
    "Current 2D NAND is already below a dozen electrons per cell, and even 3D NAND will encounter scaling limitations as lithographies shrink."

    Infineon flash, data retention vs. temperature (figure 6) and P/E cycles (figure 10)

    ( L1 cache <=4TB/s on )
    combined Xpoint and QLC raid approach

    BTW, did read about '10 years retention time on 150°C' (PCM for enhanced data storage times, A. Redaelli, Ed., Phase Change Memory), what seem being a necessity (standard) for automotive devices/tasks.

    data retention for 3DXP (3d-Xpoint) for client or enterprise flash storage devices ?

    *Thanks to all*
  • mode_13h - Wednesday, January 5, 2022 - link

    I have an old, NVME 1.0 Intel SSD that's probably MLC. Its datasheet said the same thing about a 3 month limit for power-off data retention, but I've left it powered off for probably close to 6 months at a time and lost nothing. I think that's just their minimum guarantee. I use BTRFS, which maintains per-block checksums that enable me to be fairly certain no (uncorrectable) bit-fade occurred.
  • back2future - Wednesday, January 5, 2022 - link

    researching was more about learning how flash cells technology improved and reality is better experience than theoretical limits, yes
    read endurance is some research work, but what to learn (common knowledge) for new consumer devices on QLC (2022) technology (different from professionals enterprise/datacenter storage devices and (data) maintenance knowledge)?
    People (did) change from HDDs towards SSDs ...
  • Jaaap - Wednesday, December 15, 2021 - link

    It has a 10-year retention time *at 150C* vs 100 seconds for normal NAND.
  • Kamen Rider Blade - Wednesday, December 15, 2021 - link

    When you archive data, who stores their physical media @ 150° C?

    Most people don't do that.
  • Eletriarnation - Wednesday, December 15, 2021 - link

    This is true, but high endurance in extreme conditions can often imply extreme endurance in normal conditions. See also: the recent scandal about extreme-cold steel tests for US submarines.
  • Kamen Rider Blade - Wednesday, December 15, 2021 - link

    The person who faked the Metallurgy tests deserves the full force of the law thrown against them.
  • ballsystemlord - Wednesday, December 15, 2021 - link

    Spelling and grammar errors:

    "The company says that a standard modern memory cell with this level of control would only be able to retail the data for around 100 seconds,..."
    "retain", not "retail":
    "The company says that a standard modern memory cell with this level of control would only be able to retain the data for around 100 seconds,..."

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