TSMC has introduced a brand-new manufacturing technology roughly every two years over the past decade. Yet as the complexity of developing new fabrication processes is compounding, it is getting increasingly difficult to maintain such a cadence. The company has previously acknowledged that it will start producing chips using its N3 (3 nm) node about four months later than the industry is used to (i.e., Q2), and in a recent conference call with analysts, TSMC revealed additional details about its latest process technology roadmap, focusing on their N3, N3E, and N2 (2 nm) technologies.

N3 in 2023

TSMC's N3 technology will provide full node scaling compared to N5, so its adopters will get all performance (10% - 15%), power (-25% ~ -30%), and area (1.7x higher for logic) enhancements that they come to expect from a new node in this day and age. But these advantages will come at a cost. The fabrication process will rely extensively on extreme ultraviolet (EUV) lithography, and while the exact number of EUV layers is unknown, it will be a greater number of layers than the 14 used in N5. The extreme complexity of the technology will further add to the number of process steps – bringing it toto well over 1000 – which will further increase cycle times. 

As a result, while mass production of the first chips using TSMC's N3 node will begin in the second half of 2022, the company will only be shipping them to an undisclosed client for revenue in the first quarter of 2023. Many observers, however, expected these chips to ship in late 2022.

"N3 risk production is scheduled in 2021, and production will start in second half of 2022," said C.C. Wei, CEO of TSMC. "So second half of 2022 will be our mass production, but you can expect that revenue will be seen in first quarter of 2023 because it takes long — it takes cycle time to have all those wafer out."

N3E in 2024

Traditionally, TSMC offers performance-enhanced and application-specific process technologies based on its leading-edge nodes several quarters after their introduction. With N3, the company will be changing their tactics somewhat, and will introduce a node called N3E, which can be considered as an enhanced version of N3. 

This process node will introduce an improved process window with performance, power, and yield enhancements. It is unclear whether N3 meets TSMC's expectations for PPA and yield, but the very fact that the foundry is talking about improving yields indicates that there is a way to improve it beyond traditional yield boosting methods. 

"We also introduced N3E as an extension of our N3 family," said Wei. "N3E will feature improved manufacturing process window with better performance, power and yield. Volume production of N3E is scheduled for one year after N3."

TSMC has not commented on whether N3E will be compatible with N3's design rules, design infrastructure, and IPs. Meanwhile, since N3E will serve customers a year after N3 (i.e., in 2024), there will be quite some time for chip designers to prepare for the new node.

N2 in 2025

TSMC's N2 fabrication process has largely been a mystery so far. The company has confirmed that it was considering gate-all-around field-effect transistors (GAAFETs) for this node, but has never said that the decision was final. Furthermore, it has never previously disclosed a schedule for N2. 

But as N2 gets closer, TSMC is slowly locking down some additional details. Particularly, the company is now formally confirming that the N2 node is scheduled for 2025. Though they are not elaborating on whether this means HVM in 2025, or shipments in 2025.

"I can share with you that in our 2-nm technology, the density and performance, will be the most competitive in 2025," said Wei.

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  • liahos1 - Monday, October 18, 2021 - link

    So it seems even the mighty TSM is not without their mistakes...
  • melgross - Monday, October 18, 2021 - link

    What mistakes? Remember that initial schedules are just estimates. As it gets closer, final dates become clearer. It’s never sooner, always a bit later. Nothing new about that.

    What’s amazing is that 3nm can be done at all, much less 2nm, which seems insane.
  • FreckledTrout - Monday, October 18, 2021 - link

    TSMC's 2nm using GAA is going to be insane especially for SRAM density. When Intel//Samsung/TSMC are all on there GAA nodes densities will allow all sorts of fun like good gaming APU's.
  • Yojimbo - Monday, October 18, 2021 - link

    TSMC isn't just "estimating" introducing a node for the Apple order. That's a goal. If they miss it it's a failure. There have been at least one and possibly two delays associated with 3 nm now. First the Apple order was missed, and now probably another, since they are only recognizing revenue in 2023. At least they are giving more clarity on the extent of the delay and it's bigger than many were anticipating. It's looking a bit like a 6 month delay now.
  • Curiousland - Monday, October 18, 2021 - link

    Revenue in 2023 means process start in 4Q2021 since it takes 3+ months get N3 chips finished from start. So the timeline of 2H2021 mass production is met.
  • Yojimbo - Monday, October 18, 2021 - link

    I don't know the normal revenue-recognition for TSMC, but I doubt it's 3 months from wafer start. The "timeline is met". In other words, it can be spun.. Mass production was supposed to start in Q2. Then it was 2H 2022. Now it apparently will be Q4. But when in Q4? Since revenue recognition won't take place until 2023 it's likely not early Q4. Who knows, maybe it will be December 20th 2022? That will "meet the timeline". Or, now that they've shifted from talking about 2H 2022 production to Q1 2023 revenue recognition they don't need to actually have volume production start in 2022 at all to "meet the timeline". When they successfully start recognizing the revenue in Q1 2023 they will declare success regardless.
  • whatthe123 - Tuesday, October 19, 2021 - link

    They named 2H 2022 as the shipment date because that's Apple's cadence. they have missed the date, there's no dancing around it.
  • TheJian - Wednesday, November 3, 2021 - link

    Didn't miss the date if apple just didn't buy enough 3nm to launch with NOT figuring Intel would jump in and buy as much 3nm as possible to screw all involved. Brilliant. :) Apple is dancing because they thought they had 3nm for macs next year, now AMD is dancing because apple took the 4nm they hoped to have. My guess is AMD is least prepared to deal with what has happened in the last 6-9 months. NV/Intel/Apple just launch other parts they have stored up just in case of crap like this. AMD on the other hand does each design as needed pretty much. They don't have the NET INCOME to FART around with test projects or just in case designs. Now NV is coming back big for gpu at TSMC also, so everyone is WAFER-FU fighting...LOL. Good times. Intel/MU probably both crack 100 before next xmas (not this year, DDR5 rollout etc next year causes it, higher margin new junk to pitch).

    Tesla 4000 by 2025 end. 10K by 2030. :) Unless the govt figures out how to kill him, or big pharma, food industry, unions, battery makers, car makers, battery pack makers, etc etc etc...Jeez, this guy better have good protection, trying to take out wasteful multi-billion dollar markets can be VERY dangerous. These people at the FDA, FBI, CIA, NSA, DOJ etc etc, all have no problem knocking off anyone that gets in their POWER way. They have all proven themselves to be ENEMIES of the state run probably by vatican/soros etc from DC (that little place that is a vatican business, running the fake USA). hmm...Just saying. 1870act/1871 act....You have to look up the first act to get what they really did in the 2nd. Traitors.
  • Santoval - Monday, October 25, 2021 - link

    'There is plenty of room at the bottom' but not *that* much room left. The limits of quantum mechanics are either an enemy (for conventional FETs) or a friend (for quantum FETs, or QFETs, which employ quantum tunneling).

    QFETs work better, not worse, with cutting edge nodes because their very fine features make quantum tunneling easier and more efficient. Although they employ quantum tunneling (QT) they are not quantum computers; they use QT as an optimization technique at the transistor level, not as a high level operating principle.

    Even QFETs, though, have size limits. And before those limits are reached the economics of building fabs with.. subarmstrong process nodes will stop making sense, since they will always have a negative ROI.
  • geoxile - Monday, October 18, 2021 - link

    It wasn't that many generations ago when Intel appeared to be the untouchable leader, or when Samsung 14nm was beating TSMC 16nm on apple chips. Anything can happen and a single node can make all the difference.

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