At next week’s annual VLSI Symposium, Intel will be presenting a trio of highly-anticipated papers about their progress with their upcoming PowerVia chip fabrication technology – the company’s in-development implementation of backside power delivery networks. Along with Intel’s RibbonFET technology for gate-all-around transistors, PowerVia and RibbonFET are slated to serve as Intel’s big one-two punch to the rest of the silicon lithography industry, introducing two major chip technologies together that Intel believes will vault them back into the fab leadership position. Combined, the two technologies are going to be the backbone of Intel’s “angstrom” era fab nodes, which will go into high volume manufacturing next year, making Intel’s progress with the new technologies a subject of great importance both inside and outside of the...
AnandTech Interview with Dr. Ann Kelleher: EVP and GM of Intel’s Technology Development
It’s somewhat of an understatement to say that Intel’s future roadmap on its process node development is one of the most aggressive in the history of semiconductor design. The...13 by Dr. Ian Cutress on 2/18/2022
Bringing Geek Back: Q&A with Intel CEO Pat Gelsinger
One of the overriding key themes of Pat Gelsinger’s ten-month tenure at Intel has been the eponymous will to ‘bring geek back’ to the company, implying a return to...49 by Dr. Ian Cutress on 10/29/2021
Intel’s First High-Profile IFS Fab Customer: Qualcomm Jumps on Board For 20A Process
Alongside Intel’s sizable announcement today regarding their manufacturing roadmap over the next half-decade, the company is also announcing their first major customer for their third-party foundry service, IFS. And...59 by Ryan Smith on 7/26/2021
Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!
In today’s Intel Accelerated event, the company is driving a stake into the ground regarding where it wants to be by 2025. CEO Pat Gelsinger earlier this year stated...326 by Dr. Ian Cutress on 7/26/2021