Memory Performance: 16GB DDR3-1333 to DDR3-2400 on Ivy Bridge IGP with G.Skill
by Ian Cutress on October 18, 2012 12:00 PM EST- Posted in
- Memory
- G.Skill
- Ivy Bridge
- DDR3
As mentioned in the DDR3-1600 kit, as processors develop the manufacturers raise the minimum speed to which those processors and memory controllers are rated. This means that higher speed memory kits are guaranteed, and as such the market has to adjust – with the high end Trinity processors supporting DDR3-1866 out of the box, the rest of the spectrum will rise to cover this. As a result, the memory manufacturers have to argue for better deals over their ICs, and make sure the design of the ICs will secure higher yields of the faster stuff which they can sell on to the users. Our leap from DDR3-1600 to DDR3-1866 is a leap from an $80 kit to a $95 kit, or an increase in ~19% in the price.
Visual Inspection
The Sniper kits are the oddest of G.Skill’s lineup. As we can see in the images below, the heatsink is shaped like a rifle. Bonus points if you can tell us what rifle it is meant to be. The benefits of having a rifle as a heatsink may point towards building a Gigabyte G-series system or MSI Big Bang XPower rig, both of which take designs using weapons as part of the standard. Apart from this, there is not much benefit to a stylized heatsink such as this – heat dissipation will be similar to the other kits in this review, and the main reason for this heatsink is to protect the user and competition from knowing what ICs are under the hood.
As with the RipjawsX kit, I placed a module of the kit in our system with the TRUE Copper, just to see the effect of having a large air cooler would have on the nearest memory module on a motherboard:
Again due to the height of the module, large air coolers that impinge on the memory slots will cause the Sniper kits to be placed at an angle.
JEDEC + XMP Settings
| G.Skill | |||||
| Kit Speed | 1333 | 1600 | 1866 | 2133 | 2400 |
| Subtimings | 9-9-9-24 2T | 9-9-9-24 2T | 9-10-9-28 2T | 9-11-10-28 2T | 10-12-12-31 2T |
| Price | $75 | $80 | $95 | $130 | $145 |
| XMP | No | Yes | Yes | Yes | Yes |
| Size | 4 x 4 GB | 4 x 4 GB | 4 x 4 GB | 4 x 4 GB | 4 x 4 GB |
|
|
|||||
| MHz | 1333 | 1600 | 1867 | 2134 | 2401 |
| Voltage | 1.500 | 1.500 | 1.500 | 1.650 | 1.650 |
| tCL | 9 | 9 | 9 | 9 | 10 |
| tRCD | 9 | 9 | 10 | 11 | 12 |
| tRP | 9 | 9 | 9 | 10 | 12 |
| tRAS | 24 | 24 | 28 | 28 | 31 |
| tRC | 33 | 33 | 37 | 38 | 43 |
| tWR | 10 | 12 | 14 | 16 | 16 |
| tRRD | 4 | 5 | 5 | 6 | 7/6 |
| tRFC | 107 | 128 | 150 | 171 | 313 |
| tWTR | 5 | 6 | 8/7 | 9/8 | 10/9 |
| tRTP | 5 | 6 | 8/7 | 9/8 | 10/9 |
| tFAW | 20 | 24 | 24 | 25 | 26 |
| tCWL | - | 7 | 7 | 7 | 7 |
| CR | - | 2 | 2 | 2 | 2 |
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frozentundra123456 - Thursday, October 18, 2012 - link
While interesting from a theoretical standpoint. I would have been more interested in a comparison in laptops using HD4000 vs A10 to see if one is more dependent on fast memory than others. To be blunt, I dont really care much about the IGP on a 3770K. It would have been a more interesting comparison in laptops where the igp might actually be used for gaming. I guess maybe it would have been more difficult to do with changing memory around so much in a laptop though.The other thing is I would have liked to see the difference in games at playable frame rates. Does it really matter if you get 5.5 or 5.9 fps? It is a slideshow anyway. My interest is if using higher speed memory could have moved a game from unplayable to playable at a particular setting or allowed moving up to higher settings in a game that was playable.
mmonnin03 - Thursday, October 18, 2012 - link
RAM by definition is Random Access which means no matter where the data is on the module the access time is the same. It doesn't matter if two bytes are on the same row or on a different bank or on a different chip on the module, the access time is the same. There is no sequential or random difference with RAM. The only difference between the different rated sticks are short/long reads, not random or sequential and any reference to random/sequential reads should be removed.Olaf van der Spek - Thursday, October 18, 2012 - link
You're joking right? :pmmonnin03 - Thursday, October 18, 2012 - link
Well if the next commenter below says their memory knowledge went up by 10x they probably believe RAM reads are different depending on whether they are random or sequential.nafhan - Thursday, October 18, 2012 - link
"Random access" means that data can be accessed randomly as opposed to just sequentially. That's it. The term is a relic of an era where sequential storage was the norm.Hard drives and CD's are both random access devices, and they are both much faster on sequential reads. An example of sequential storage would be a tape backup drive.
mmonnin03 - Thursday, October 18, 2012 - link
RAM is direct access, no sequential or randomness about it. Access time is the same anywhere on the module.XX reads the same as
X
X
Where X is a piece of data and they are laid out in columns/rows.
Both are separate commands and incure the same latencies.
extide - Thursday, October 18, 2012 - link
No, you are wrong. Period. nafhan's post is correct.menting - Thursday, October 18, 2012 - link
no, mmonnin03 is more correct.DRAM has the same latency (relatively speaking.. it's faster by a little for the bits closer to the address decoder) for anywhere in the memory, as defined by the tAA spec for reads. For writes it's not as easy to determine since it's internal, but can be guessed from the tRC spec.
The only time that DRAM reads can be faster for consecutive reads, and considered "sequential" is if you open a row, and continue to read all the columns in that row before precharging, because the command would be Activate, Read, Read, Read .... Read, Precharge, whereas a "random access" will most likely be Activate, Read, Precharge most of the time.
The article is misleading, using "sequential reads" in the article. There is really no "sequential", because depending if you are sequential in row, column, or bank, you get totally different results.
jwilliams4200 - Thursday, October 18, 2012 - link
I say mmonnin03 is precisely wrong when he claims that " no matter where the data is on the module the access time is the same".The read latency can vary by about a factor of 3 times whether the read is from an already open row, or whether the desired read comes from a different row than one already open.
That makes a big difference in total read time, especially if you are reading all the bytes in a page.
menting - Friday, October 19, 2012 - link
no. he is correct.if every read has the conditions set up equally (ie the parameters are the same, only the address is not), then the access time is the same.
so if address A is from a row that is already open, the time to read that address is the same as address B, if B from a row that is already open
you cannot have a valid comparison if you don't keep the conditions the same between 2 addresses. It's almost like saying the latency is different between 2 reads because they were measured at different PVT corners.