Which is literally the goal of all of these new memory technologies, to becomes Storage Class Memories: all of the performance of DRAM without volatility.
Most technologies are still a lower density than DRAM because DRAM is so simple. Each bit is a single MOS transistor tied to a reasonable capacitance. CMOS is insanely mature from a process standpoint, unlike all of these new devices like MRAM, memristors, and phase-change memories. As all of these technologies catch up to CMOS, they will definitely exceed the density of DRAM per unit area. For now though, DRAM density scales easily with each new process node and we really haven't taken advantage of 3D dies.
I don't know much about these new memories (obviously) how will they exceed the density of DRAM, given that (as you note) DRAM is such a simple structure?
The building blocks are physically smaller than DRAM cells on the same node. Right now it's more of an issue of how to reliably improve the matching between these new elements. We are very good at doing this with CMOS devices, but new tech is still behind.
There's also other interesting aspects of these new devices which allow them to store multiple bits per cell. Memristors have so far been shown to have dozens of states which makes it easier to consider 4+bits per cell. They are also a lot easier to design crossbar structures for, which means that 3D storage can be accomplished without expensive die-stacking. This is not dissimilar to 3D NAND devices, just at higher densities and theoretically lower power.
"The building blocks are physically smaller than DRAM cells on the same node. "
Not just that, when/if we get there, but that by eliminating one or more of the hops to 'cold' storage you eliminate other devices, their power, their controllers, etc. Also, for apps that use controlled data storage, e.g. RDBMS, many (most?) of those apps could run on-line without all those caches to be managed, as well. Periodic backup to SSD/HDD/CDROM/tape will still be part of the protocol, of course.
The biggest hit to system building will be expanding the cpu/MB address space support all the way to 64 bits. Imagine DB2 run on a single-level datastore? Just what Codd had in mind 50 years ago.
Because FLASH on its own isn't very fast or low enough latency. Most of the current gen of NVDIMMs (excluding 3D XPoint) use DRAM most of the time and then dump that data to FLASH on a power loss. They serve to prevent data loss, not to speed up workloads. Everything else is still catching up in density and cost to FLASH.
"As all of these technologies catch up to CMOS, they will definitely exceed the density of DRAM per unit area." 3D XPoint is a type of phase-change memory (or, according to others, a ReRAM memory) and due to the way it's designed it can have 4 times the density of DRAM at the same node. It's nowhere close in latency though. High density alone is not enough to displace DRAM. High density, DRAM rivaling latency *and* comparable cost are required for that (non volatility as well, of course, which all modern kinds of memory tend to have).
Given Microns involvement, I'm fairly certain 3D XPoint is PCM, yeah. Sorry, when I said performance, I was talking about throughput, latency, and power-efficiency. I didn't think I needed to address cost because it should be obvious that most new technologies are more expensive than mature ones. The Intel P4800X has 10us of latency, which is literally 100x better than the ~1-5ms of most FLASH devices and accomplished without a DRAM cache. I recognize that that is still about 1000x higher than DRAM latency, but it's a hell of a start for such a new technology.
True enough, but something like this (non-volatile RAM) would add a level of reliability that SD cards don't have. Yes, they're 'good enough', but if we could have at least a SATA (port multiplier capable) interface for bulk storage I could see these becoming incredibly useful.
Build your own NAS, build your own Smart TV, etc...
(STT-)MRAM is significantly faster than NAND flash, much faster even than Intel/Micron's 3D XPoint - though in the above example it is probably bottlenecked by the interface, which is both very narrow and low clocked. It is marginally slower than DRAM actually (at high densities) and even faster than DRAM - almost as fast as SRAM (at low densities), while its non volatility and very impressive power efficiency are surely worth the trade-off of somewhat lower performance at high density (or nodes from ~20nm and below, it's the same thing). While 3D XPoint has a latency in the 3 - 15 microsecond range, (STT-)MRAM can have a latency from a blazing fast 2 ns up to ~200 ns, depending on the density.
Will anandtech be doing an article explaining what MRAM is and how it works?! This is very exciting stuff and it looks like you might be able to do more than you did for Optane. PS: Wikipedia is unhelpful.
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19 Comments
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nandnandnand - Monday, June 24, 2019 - link
So it's non-volatile, but less dense and slower than DRAM.We could use something that is non-volatile, near DRAM speeds, and as denser or more dense than NAND. Then we can have universal memory.
SaberKOG91 - Monday, June 24, 2019 - link
Which is literally the goal of all of these new memory technologies, to becomes Storage Class Memories: all of the performance of DRAM without volatility.Most technologies are still a lower density than DRAM because DRAM is so simple. Each bit is a single MOS transistor tied to a reasonable capacitance. CMOS is insanely mature from a process standpoint, unlike all of these new devices like MRAM, memristors, and phase-change memories. As all of these technologies catch up to CMOS, they will definitely exceed the density of DRAM per unit area. For now though, DRAM density scales easily with each new process node and we really haven't taken advantage of 3D dies.
rpg1966 - Monday, June 24, 2019 - link
I don't know much about these new memories (obviously) how will they exceed the density of DRAM, given that (as you note) DRAM is such a simple structure?SaberKOG91 - Tuesday, June 25, 2019 - link
The building blocks are physically smaller than DRAM cells on the same node. Right now it's more of an issue of how to reliably improve the matching between these new elements. We are very good at doing this with CMOS devices, but new tech is still behind.There's also other interesting aspects of these new devices which allow them to store multiple bits per cell. Memristors have so far been shown to have dozens of states which makes it easier to consider 4+bits per cell. They are also a lot easier to design crossbar structures for, which means that 3D storage can be accomplished without expensive die-stacking. This is not dissimilar to 3D NAND devices, just at higher densities and theoretically lower power.
rpg1966 - Tuesday, June 25, 2019 - link
Excellent, thank you.FunBunny2 - Tuesday, June 25, 2019 - link
"The building blocks are physically smaller than DRAM cells on the same node. "Not just that, when/if we get there, but that by eliminating one or more of the hops to 'cold' storage you eliminate other devices, their power, their controllers, etc. Also, for apps that use controlled data storage, e.g. RDBMS, many (most?) of those apps could run on-line without all those caches to be managed, as well. Periodic backup to SSD/HDD/CDROM/tape will still be part of the protocol, of course.
The biggest hit to system building will be expanding the cpu/MB address space support all the way to 64 bits. Imagine DB2 run on a single-level datastore? Just what Codd had in mind 50 years ago.
sonicmerlin - Tuesday, June 25, 2019 - link
Then why are they still selling 4 or 8 GB RAM modules while SSDs have scaled into multi terabytes?SaberKOG91 - Wednesday, June 26, 2019 - link
Because FLASH on its own isn't very fast or low enough latency. Most of the current gen of NVDIMMs (excluding 3D XPoint) use DRAM most of the time and then dump that data to FLASH on a power loss. They serve to prevent data loss, not to speed up workloads. Everything else is still catching up in density and cost to FLASH.sonicmerlin - Friday, June 28, 2019 - link
But DRAM has existed for decades, why haven't we seen it scale up over the last several years at the pace of Moore's Law?Santoval - Tuesday, June 25, 2019 - link
"As all of these technologies catch up to CMOS, they will definitely exceed the density of DRAM per unit area."3D XPoint is a type of phase-change memory (or, according to others, a ReRAM memory) and due to the way it's designed it can have 4 times the density of DRAM at the same node. It's nowhere close in latency though. High density alone is not enough to displace DRAM. High density, DRAM rivaling latency *and* comparable cost are required for that (non volatility as well, of course, which all modern kinds of memory tend to have).
SaberKOG91 - Wednesday, June 26, 2019 - link
Given Microns involvement, I'm fairly certain 3D XPoint is PCM, yeah. Sorry, when I said performance, I was talking about throughput, latency, and power-efficiency. I didn't think I needed to address cost because it should be obvious that most new technologies are more expensive than mature ones. The Intel P4800X has 10us of latency, which is literally 100x better than the ~1-5ms of most FLASH devices and accomplished without a DRAM cache. I recognize that that is still about 1000x higher than DRAM latency, but it's a hell of a start for such a new technology.Threska - Monday, June 24, 2019 - link
The new Raspberry Pi could have used something like this.nandnandnand - Monday, June 24, 2019 - link
Is this the "no eMMC" complaint? The maximum microSD performance is doubled from the previous version, which should be good enough for most users.bill.rookard - Tuesday, June 25, 2019 - link
True enough, but something like this (non-volatile RAM) would add a level of reliability that SD cards don't have. Yes, they're 'good enough', but if we could have at least a SATA (port multiplier capable) interface for bulk storage I could see these becoming incredibly useful.Build your own NAS, build your own Smart TV, etc...
Santoval - Tuesday, June 25, 2019 - link
(STT-)MRAM is significantly faster than NAND flash, much faster even than Intel/Micron's 3D XPoint - though in the above example it is probably bottlenecked by the interface, which is both very narrow and low clocked.It is marginally slower than DRAM actually (at high densities) and even faster than DRAM - almost as fast as SRAM (at low densities), while its non volatility and very impressive power efficiency are surely worth the trade-off of somewhat lower performance at high density (or nodes from ~20nm and below, it's the same thing).
While 3D XPoint has a latency in the 3 - 15 microsecond range, (STT-)MRAM can have a latency from a blazing fast 2 ns up to ~200 ns, depending on the density.
Mr.Vegas - Sunday, June 30, 2019 - link
Like 3D Xpoint for example?.ksec - Tuesday, June 25, 2019 - link
Price. How much do they cost? This will fundamentally determine its usage.BMNify - Tuesday, June 25, 2019 - link
see the older parts specs prices etc assuming they will also sold herehttps://www.mouser.co.uk/Everspin-Technologies/fea...
ballsystemlord - Monday, July 1, 2019 - link
Will anandtech be doing an article explaining what MRAM is and how it works?! This is very exciting stuff and it looks like you might be able to do more than you did for Optane.PS: Wikipedia is unhelpful.