Intel Details Manufacturing through 2023: 7nm, 7+, 7++, with Next Gen Packagingby Ian Cutress & Anton Shilov on May 8, 2019 4:35 PM EST
At Intel's Investor Day today, CEO Bob Swan and Murthy Renduchintala spoke to the ability of the company with respect to its manufacturing capabilities. Intel has historically been strong in its ability to execute on its process technology, however the delay of its 10nm process has obviously raised multiple question marks, and has done for several years. The two Intel executives went into a little detail about what Intel was doing in the interim, and how it has learned from the issues.
Back in 2013, Intel envisoned its 10nm to succeed the 14nm by providing 2.7x density, with new technologies such as Self-Aligned Quad Patterning (SAQP), Contact over Active Gate (COAG), Cobolt Interconnects, and new packaging technologies such as EMIB and Foveros. Intel admits that this was an ambitious plan, and the goals were not clearly defined with the teams and it was ultimately overly complex and not managed in an ideal way.
This ended up pushing 10nm out into a later time frame. In this case, Intel pushed 10nm out to 2019 (technically they shipped Cannon Lake in small quantities on 10nm in 2017, however that is nothing more than a curio in the timeline of semiconductors), and filled the gap with 14+ and 14++.
Intels 14+ and 14++ processes extracted more than 20% more performance (from Broadwell to Whiskey Lake) from the process since its inception. As a result, Intel is prepared to not only get ready for future intra-node optimizations, but actually adjust the roadmap to compensate for it. Murthy made it clear that Intel wants to introduce a Moore's Law-like gain at the beginning of a new process, and another similar gain by the end of the process.
Intel has stated that its 10nm product family (beyond Cannon Lake) will start to be available from the middle of this year (2019), with Ice Lake on client platforms (notebooks).
Intel will be launching multiple 10nm products through 2019 and 2020, including server based 10nm in the first half of 2020:
In the above slide, Intel states that it will have 7nm in production and launching a product in 2021. That sounds very aggressive for a company that has had issues with 10nm. It even shows in Intels radmap, with 10nm (and 10+ and 10++) having a much shorter life cycle than the 14nm family of processes.
With this in mind, Intel's 7nm is going to be the combination of what Intel has learned from the 14nm and 10nm family of products. Intel wants that 2x scaling (Moores Law), but with intra-node optimations planned as part of the roadmap. Intel is also reducing its number of design rules, which should help with execution. 7nm will also be where Intel intersects with EUV, and also introduce next-gen Foveros and EMIB packainging.
Intel provided this slide, which shows a monolithic PC-Centric die with a multi-die Data-Centric chip built on both Foveros and EMIB. This corroborates our discussion with Intel's chiplet and packaging team, who also stated that we would see Foveros and EMIB on a combined product - specifically the GPU.
Intel announced that its lead 7nm product (lead = top, or lead = first?) would be its new GPGPU, built on the Xe graphics architecture. Intel has stated that its Xe product stack will feature two different microarchitectures from mobile client up to GPGPU, with one of those architectures called Arctic Sound - technically Intel will launch its first discrete GPU in 2020 according to its press release, however the 7nm GPGPU will be launched in 2021.
More information is coming out of Intel's Event, more to follow.
- Intel: EUV-Enabled 7nm Process Tech is on Track
- Intel Starts Qualification of Ice Lake CPUs, Raises 10nm Volume Expectation for 2019
- Intel Agilex: 10nm FPGAs with PCIe 5.0, DDR5, and CXL
- Intel to Equip Fab 42 for 7 nm
- Intel Discloses Plans to Spend $5 Billion on Fab 28 Expansion in Israel
- Intel Submits Ireland Fab Expansion Plan: $8 Billion Price Tag, With a 4 Year Lead Time
- Intel Details Plans for Its Oregon Fab Expansion: D1X Phase 3
- Intel to Expand Production Capacities at Multiple Fabs
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abufrejoval - Wednesday, May 8, 2019 - linkSeeing is believing.
And then the ability to put more transistors into a die is nothing by itself, unless it yields tangible value.
2.x density won't deliver 2.x IPC or 1/2.x power consumption.
Not holding my breath...
peevee - Wednesday, May 8, 2019 - linkAnd not 1/2 of cost.
And not even 2x density ("7" vs "10"), I suspect.
Bluetooth - Wednesday, May 8, 2019 - linkDensity is in the power of two: 10^2 / 7^2 = 2x
peevee - Thursday, May 9, 2019 - linkIf only the "7" and "10" had anything to do with reality... for about 10 years now these are purely marketing BS.
psychobriggsy - Thursday, May 9, 2019 - linkYes, but the MTr/mm^2 figures are a reasonable guideline to density, these are off the top of my head:
Intel 14nm, TSMC/SS 10nm: About 35-40MTr/mm^2
Samsung 8nm: ~60MTr/mm^2
Samsung 7nm: 95MTr/mm^2
TSMC 7nm: 96MTr/mm^2
TSMC N7+: 114MTr/mm^2
TSMC N5: ~170MTr/mm^2
Intel 10nm: 102MTr/mm^2 but they haven't given any figures for what their shipping 10nm will be
Intel 7nm: "2X" 10nm, so ~200MTr/mm^2 (likely competing against N5 or N5+)
Dolan - Friday, May 10, 2019 - linkThis is theory based on Intel's promises.
Now little reality:
Intel 14 = other 14/16 ... https://images.anandtech.com/doci/11170/ISSCC%208....
Intel 10 = other 10 ... use of SAQP, LE3/4...
Intel 7 = other 7 ... EUV versions
Seriously people, Its Intel... They are lying.
Azethoth - Saturday, May 11, 2019 - linkYou are confused about how these things compare. Historically nobody matched Intel with actual density being the same at the marketing numbers. Your claims are false and known to be false.
Butterfish - Saturday, May 11, 2019 - link@Dolan Your graph doesn’t show anything that supports your argument if anything it actually show Intel has smaller transistor. Even if you don’t like MT/mm2 matrix using traditional CPPxMMP and plug in the figure in your graph. Intel is still 1.4X denser very similar to 1.5X denser reported in real world.
0ldman79 - Sunday, May 19, 2019 - linkIt also shows that twice the L2 takes up 50% more space on the supposedly weaker process.
Their transistors are similar.
It doesn't show the actual chip density, however, Intel's 10nm chip density is like 20-30% higher than TSMC's 7nm (ballpark), however, TSMC is shipping 7nm product. Intel is not.
At the end of the day which one is tighter doesn't really matter, it matters whether the product works as advertised. 10nm vs 7nm, maybe Intel's 10nm really is a better design, but they don't work. Yields were in the single digits for Cannon Lake.
Spunjji - Wednesday, May 22, 2019 - linkNailed it. A node that won't yield or perform to spec is a bad node, no matter how dense.