In the realm of processor and product design, having the right series of tools to actually build and simulate a product has been a key driver in minimizing time to market. Cadence is one of the more prolific companies in the electronic design automation (EDA) software space, with tools for designing integrated circuits, PCBs, packaging, SoCs, radio frequency, as well as respective verification tools. What landed in my inbox this morning was an announcement for a new tool in Cadence’s solver portfolio to enable better full-system EM simulation while also scaling across CPU and GPU as well as to other systems.

Cadence’s 3D Transient Solver uses a finite difference time domain model to essentially model an anechoic chamber over a wide frequency range for both electromagnetic interference but also electromagnetic compliance. This is what the EC/FCC certification enablement is all about in order to enable sales of a product in a region – the more accurate (and scalable) the EM simulation work is, the idea is that the results from any anechoic chamber testing will be more in line with the simulation, resulting in fewer prototype sampling in advance of the certification test.

The Transient Solver is designed to work in conjunction with Cadence’s other tools, such as FEM and MoM, for whole product simulation – due to capacity, it has often been the case that products would be simulated part-by-part, and then a full scale simulation result would be interpolated. Cadence points to its full product potential, as the software is designed to scale almost linearly across as many CPU cores as can be thrown at it (either in a single system or in a multi-system environment), as well as leveraging GPU acceleration (note, something I did in my PhD for FDTD but for chemical simulations). Cadence also points to its ability to keep the simulation memory footprint low, often a difficult task with these sorts of simulations (especially FDTD), such that systems no longer need terabytes of DRAM just to run. The software can also be run via cloud services and scaled as needed. Due to the scalability, it also allows for quicker deformation testing, to avoid such areas as the iPhone 4 issues.

Anechoic chambers are marvellous things – if you ever get a chance to go in one, I highly recommend it. If the 30% reduced cycle time that one of Cadence’s partners is quoting is anything to go by, then there might be some chambers empty for a bit – perfect to get your company to convince that an employee tour is needed.

Cadence’s Clarity 3D Transient Solver is due for release in Q1 2021.

Source: Cadence

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  • SokraMA - Monday, October 19, 2020 - link

    There have been plenty of new tools from the big 3 EDA vendors (Cadence, Synopsis & Mentor), but they’re not featured on Anandtech and probably aren’t in its focus. This article sounds like an ad... Reply
  • Ian Cutress - Monday, October 19, 2020 - link

    All our sponsored posts are clearly marked as such.

    I've been signed up to the breakfast bytes newsletter from Cadence for quite a while and get weekly updates. I don't follow them that closely, but this one was in my inbox this morning, so I wrote it up as it seemed interesting. The odd post here and there piques my interest, especially as my background is in simulation. Same way as I sometimes post about Xilinx, when I see something of interest. I don't have weekly updates from the other EDA tool vendors.
    Reply
  • webdoctors - Monday, October 19, 2020 - link

    Is there a reason you didn't compare it to Primetime? Or this is not a static timing analysis tool?

    This really sounds like a PR post....
    Reply
  • lmcd - Tuesday, October 20, 2020 - link

    Is there a reason you didn't delete your pointless drivel? Or this is not a self-curated forum?

    This really sounds like a 4th grader....
    Reply
  • vFunct - Tuesday, October 20, 2020 - link

    More EDA news here would be great. Reply
  • edzieba - Tuesday, October 20, 2020 - link

    The 3D EM aspect is probably going to be more and more prominent as stacked ICs become more common (especially those with integrated voltage regulators). Die-to-die coupling could be an enormous headache! Reply
  • HSO4 - Tuesday, October 20, 2020 - link

    This is pretty cool. I used to do these simulations in the early 2000s using a piece of software called Maxwell on Sun Ultra Sparcs for Alcatel Lucent in Raleigh NC. This software is now called Ansys HFSS. We could import our cabinet / PCB designs from Cadence into the software, but would have to significantly dumb them down or else the simulations would take weeks to run. The chips on the board were best guess "transmitters" using the highest clock frequencies that ran through each ASIC at an estimated power level.

    I got it to the point where most my simulations would take a few days and I literally had to sit around and wait.

    I did this while developing ASIC and PCB for ADSL and OC3/OC12 SONET line cards. We had a full turntable and anechoic chamber where we could compare our simulation results to the real world. I would really geek out on this.

    The point of it all was to save us lots of $$$ for when we did our actual FCC testing and qualification. It resulted in all our FCC radio interference testing passing the first time. This is the real value in solutions like this.
    Reply
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