Samsung and TSMC Roadmaps: 8 and 6 nm Added, Looking at 22ULP and 12FFC
by Anton Shilov on May 5, 2017 9:30 AM ESTNot Everyone Needs Leading Edge: TSMC’s 22 nm ULP, 12 nm FFC and 12 nm FFC+
Now let’s discuss something less advanced, but what is required for hundreds of millions of devices sold every year.
| Advertised PPA Improvements of TSMC's Low-Power/Compact Nodes Data announced by TSMC during conference calls, press briefings and in press releases |
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| CLN28HPC vs CLN28HPM |
CLN28HPC+ vs CLN28HPM |
CLN22LPU vs CLNHPC+ |
CLN16FFC vs CLN16FF |
CLN12FFC vs CLN16FFC |
12FFC-ULP vs CLN12FFC |
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| Power | 20% | 30% | 35% | lower | 25% | lower | ||
| Performance | - | 15% | 15% | unknown | 10% | unknown | ||
| Area Reduction | 10% | 10% | 10% | optional | 20% | unknown | ||
| HVM Start | started | started | 2018 | Q1 2016 | 2018 | 2019 | ||
| Note | Planar 28 nm-based |
FinFET 16/20 nm-based |
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Development of FinFET-based chips is more expensive of ICs featuring planar transistors and their manufacturing is more costly as well. As a result, FinFET is virtually unavailable for many smaller designers of SoCs that usually build various solutions for emerging IoT applications. GlobalFoundries and Samsung offer their FD-SOI manufacturing processes to such companies (and these technologies have a number of other advantages in addition to being more cost-effective), whereas TSMC intends to introduce its new 22 nm ULP technology aimed at such applications. The CLN22ULP is an optimized version of the company’s 28 nm HPC+ (high-performance compact plus) manufacturing process that has been available for a while. The 22ULP offers a 10% area reduction and either a 15% performance improvement over the 28HPC+ process, or a 35% power drop. The 22ULP process joins a family of other ultra-low-power processes offered by TSMC and will compete against GlobalFoundries 22FDX as well as Samsung’s 28 nm FD-SOI offering.
Next up is TSMC’s 12 nm FFC manufacturing technology, which is an optimized version of the company’s CLN16FFC that is set to use 6T libraries (as opposed to 7.5T and 9T libraries) providing a 20% area reduction. Despite noticeably higher transistor density, the CLN12FFC is expected to also offer a 10% frequency improvement at the same power and complexity or a 25% power reduction at the same clock rate and complexity. Further down the road, TSMC also plans to offer a ULP version of the CLN12FFC with reduced voltage, but that is going to happen only in 2018 or 2019.
Sources: Samsung, TSMC, SemiWiki (1, 2, 3).
Related Reading:
- Samsung Foundry Announces 10nm SoC In Mass-Production
- Samsung Announces Second-Gen 14nm Low Power Plus (14LPP) Process Now In Mass Production
- EUV Lithography Makes Good Progress, Still Not Ready for Prime Time
- GlobalFoundries to Expand Capacities, Build a Fab in China
- Intel to Equip Fab 42 for 7 nm
- GlobalFoundries Updates Roadmap: 7 nm in 2H 2018, EUV Sooner Than Later?
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Lodix - Friday, May 5, 2017 - link
Samsung's 10nmLPP has a 15% reduction in power consumption compared to the LPE version.Also the 10nmLPE numbers about performance and power 27/40% are compared to the previous 14nmLPE not the Plus version.
Lodix - Friday, May 5, 2017 - link
And the 10nmLPU version is aimed to Area reduction.Anton Shilov - Friday, May 5, 2017 - link
Thank you for the corrections. You are right about the 10LPP, they made and appropriate announcement a couple of weeks ago, but somehow I've missed it. Fixed.Regarding the 10LPE vs 14LP*, I am not sure.
They state the following:
"Samsung’s new 10nm FinFET process (10LPE) adopts an advanced 3D transistor structure with additional enhancements in both process technology and design enablement compared to its 14nm predecessor, allowing up to 30-percent increase in area efficiency with 27-percent higher performance or 40-percent lower power consumption."
http://www.anandtech.com/show/10765/samsung-10nm-m...
If you look at the picture there (http://images.anandtech.com/doci/10765/dac.png), they mention ~30% performance increase at the same leakage power, which can considered as 27%... But if you happen to see some more up to date slides from Samsung, please link them.
As for the 10LPU, I guess, they are going to make an announcement in late May.
Lodix - Friday, May 5, 2017 - link
I see the arrow joining the 14nmLPE version with 10nmLPE.Lodix - Saturday, May 6, 2017 - link
In this pdf from Samsung they specified that the improvements stated are from 14nmLPE and not from 14nmLPP.https://www.semiwiki.com/forum/attachments/f293/18...
MajGenRelativity - Friday, May 5, 2017 - link
I know AMD will be using GF 7nm for their GPUs after Vega 10/11, but I wonder what NVIDIA will be using after this current Pascal generation. Does anyone have any clues?haukionkannel - Friday, May 5, 2017 - link
If They Are vice They use at least two different distributors just like Apple.melgross - Saturday, May 6, 2017 - link
Apple has moved away from that model. I doubt they wanted to do it, but neither Samsung nor TSMC could produce all the SoCs they needed that year, so they had to.It's also interesting to note that while Apple had to tune their designs to both processes, the TSMC 16nm was 20% more efficient than the Samsung 14nm process. We saw results of those tests either here or on arstechnica, I don't remember which now. But the total device efficiency advantage was under 5% once everything was taken together.
But still, it shows that we can't go by theory when extrapolating these supposed numbers to the real world. I'd still rather see Apple on intel.
The_Assimilator - Friday, May 5, 2017 - link
I would be extremely surprised if it was anyone except TSMC. Especially since TSMC has just announced 10nm is ready for H2 this year - which, not coincidentally, is when NVIDIA is rumoured to drop the first Volta products.The only GPU that NVIDIA has ever sourced from a company other than TSMC is GP107 from Samsung at 14nm. Even though Sammy's 14nm node is worse than TSMC's 16nm, GP107 is such a (relatively) small and simple chip that it didn't really matter. We'll probably see a similar story with Volta: TSMC gets the big Pascals, Samsung gets the small ones.
There is, of course, always the possibility that NVIDIA will stick with the now-mature (and cheaper) 16nm for Volta - I imagine it will depend on whether Volta is more (10nm) or less (16nm) powerful clock-for-clock compared to Pascal.
Kevin G - Sunday, May 7, 2017 - link
nVidia has been flirting with Samsung of late. I doubt they'd just exclusively to Samsung but they'll likely continue to have small/medium chip there as a testing vehicle if they need to quickly switch their entire line up over.